CPU Architecture and VHDL
CPU architecture, the basic components and functionality
Parallel adders/subtractors, and multipliers, barrel shifters
VHDL modelling concepts, overview
The Dataflow/RTL model
The Structural Model
VHDL State machines
VHDL Subsets for synthesis
Design Processing
Test patterns and Simulation.
Digital Design principles
Optimisation of designs
Timing hazards
CMOS implementation of logic
Combinational Logic design Principles
Sequential Design Principles.
State machine synthesis
Use of diagrammatic tools for code synthesis
Synthesis Issues
Programmable devices, structure and function.
Synthesis process, download, testing and debugging in hardware
Developing tool chains, ancillary utilities. Use of Make, Flex etc.
Teaching and Learning Methods
This module will be presented through a combination of lectures and practicals. The practicals will provide the students with access to a VHDL development system for introductory experimentation and project work.
Individual worksheet and group-oriented practical exercises are central to the students\' experience in order to reinforce and extend the lectures and associated readings. The laboratory work includes both hardware and software, at basic unit and higher system level.
An extended case-study, supported by focussed tutorials and practicals, will allow the students to follow through an example application from design to implementation, and appreciate the relevance of all the component parts of the module syllabus. Examples of case studies could be: the design and emulation of a \'set top\' recorder such as the TiVo and the development of a custom microcontroller for remote data capture systems.